ABOUT

I am currently a security research scientist at Intel Labs. Before, I worked as a security researcher at IAIK, Graz University of Technology. After finishing my master studies in information and computer engineering at Graz University of Technology in 2013 with distinction, I joined the IAIK as a PhD student to research the security of embedded computing devices. I finished my PhD studies in 2018 as well with distinction (sub auspiciis praesidentis) with my thesis titled "Side-Channel Resistance and Pairing-based Cryptography for the Internet of Things".

My current research interests cover implementation security topics, such as (speculative) side-channel attacks, fault attacks, and their countermeasures, cryptographic implementations and protocols, and security architectures involving memory encryption, secure code execution and isolation techniques, remote attestation, and protection of intellectual property. My work encompasses finding security vulnerabilities in state-of-the-art security concepts and computing architectures, the design of efficient security architectures, the secure implementation of both hard- and software components, the evaluation of our prototypes, and the transfer of research results to future products.

PUBLICATIONS

[18] Mario Werner, Thomas Unterluggauer, Lukas Giner, Michael Schwarz, Daniel Gruss, Stefan Mangard; ScatterCache: Thwarting Cache Attacks via Cache Set Randomization; USENIX Security 2019.
[17] Mario Werner, Robert Schilling, Thomas Unterluggauer Stefan Mangard; Protecting RISC-V Processors against Physical Attacks; DATE 2019.
[16] Thomas Unterluggauer, Mario Werner, Stefan Mangard; MEAS: Memory Encryption and Authentication Secure Against Side-Channel Attacks Using Unprotected Primitives; Journal of Cryptographic Engineering (2018).
[15] Mario Werner, Thomas Unterluggauer, David Schaffenrath, Stefan Mangard; Sponge-Based Control-Flow Protection for IoT Devices; EuroS&P 2018.
[14] Robert Schilling, Thomas Unterluggauer, Stefan Mangard, Frank Gürkaynak, Michael Muehlberghuber, Luca Benini; High Speed ASIC Implementations of Leakage-Resilient Cryptography; DATE 2018.
[13] Thomas Unterluggauer, Thomas Korak, Stefan Mangard, Robert Schilling, Luca Benini, Frank Gürkaynak, Michael Muehlberghuber; Leakage Bounds for Gaussian Side Channels; CARDIS 2017.
[12] Mario Werner, Thomas Unterluggauer, Stefan Mangard; Transparent Memory Encryption and Authentication; FPL 2017.
[11] Thomas Unterluggauer, Mario Werner, Stefan Mangard; Securing Memory Encryption and Authentication Against Side-Channel Attacks Using Unprotected Primitives; ASIACCS 2017.
[10] Christoph Dobraunig, Maria Eichlseder, Stefan Mangard, Florian Mendel, Thomas Unterluggauer; ISAP-Towards Side-Channel Secure Authenticated Encryption; ToSC / FSE 2017.
[9] Thomas Unterluggauer, Mario Werner, Stefan Mangard; Side-Channel Plaintext-Recovery Attacks on Leakage-Resilient Encryption; DATE 2017.
[8] Daniel Slamanig, Raphael Spreitzer, Thomas Unterluggauer; Group Signatures with Linking-Based Revocation: A Pragmatic Approach for Efficient Revocation Checks; Mycrypt 2016.
[7] Hannes Gross, Manuel Jelinek, Stefan Mangard, Thomas Unterluggauer, Mario Werner; Concealing Secrets in Embedded Processors Designs; CARDIS 2016.
[6] Thomas Unterluggauer, Stefan Mangard; Exploiting the Physical Disparity: Side-Channel Attacks on Memory Encryption; COSADE 2016.
[5] Robert Schilling, Manuel Jelinek, Markus Ortoff, Thomas Unterluggauer; A low-area ASIC implementation of AEGIS128 - A fast authenticated encryption algorithm; Austrochip 2014.
[4] Thomas Unterluggauer, Erich Wenger; Practical Attack on Bilinear Pairings to Disclose the Secrets of Embedded Devices; ARES 2014.
[3] Thomas Unterluggauer, Erich Wenger; Efficient Pairings and ECC for Embedded Systems; CHES 2014.
[2] Daniel Slamanig, Raphael Spreitzer, Thomas Unterluggauer:; Adding Controllable Linkability to Pairing-Based Group Signatures for Free; ISC 2014.
[1] Erich Wenger, Thomas Unterluggauer, Mario Werner; 8/16/32 Shades of Elliptic Curve Cryptography on Embedded Processors; INDOCRYPT 2013.

EXPERIENCE

From 03/2019 until now
Research Scientist
2111 NE 25th Ave, Hillsboro, OR 97124, USA
From 11/2013 to 12/2018
University Assistant
Inffeldgasse 16a, 8010 Graz, Austria
From 10/2009 to 10/2013
Software Developer and Tester
Sankt-Peter-Gürtel 10b, 8042 Graz, Austria
From 04/2008 to 06/2008
Software Developer
Lakeside B01, Entrance 01A, 2nd Floor, 9020 Klagenfurt, Austria
From 08/2007 to 09/2007 and from 07/2006 to 08/2006
Internship as Software Developer (geo-information)
Europastraße 4, 9524 Villach/St. Magdalen, Austria

EDUCATION

From 03/2014 to 01/2018.
Doctoral Studies
Dissertation Topic: Side-Channel Resistance and Pairing-based Cryptography for the Internet of Things.
Rechbauerstrasse 12, 8010 Graz, Austria.
From 11/2011 to 11/2013
Master Studies in Information and Computer Engineering
Specialization: IT Security and System-On-Chip Design.
Rechbauerstrasse 12, 8010 Graz, Austria.
From 10/2008 to 11/2011
Bachelor Studies in Information and Computer Engineering
Rechbauerstrasse 12, 8010 Graz, Austria.
From 09/2002 to 06/2007
High School and School Leaving Examinations
Specialization: Electronic Data Processing and Organization - Commercial Data Processing
Tschinowitscher Weg 5, 9500 Villach, Austria.

LANGUAGE SKILLS

  • German Mother Language
  • English Proficiency